Universal PHYTM
Chiplet PHY's are currently available for standard packaging or expensive interposers.
Our PHY supports advanced packaging down to 20 u pitch and offers ultra low power and cost.
Our PHY Solution supports:
20 u pitch
20X lower area than UCIe SP
Less than 0.1 pj/bit power
BIST for KGD
Broad foundry support from 28nm down to advanced FinFet nodes.
We can support Custom Foundry Nodes if needed.
Enabling Mass Market Chiplets
Its about Cost, Power, and Faster time to market for nex-gen solutions. Yorchip's technology is focused on enabling edge markets to deploy custom silicon faster by re-using small low cost Chiplets.
We enable Chiplets that typically cost under $0.50 in volume each for CPU, ADC/ADC, standard I/O etc.
Contact us to learn more:
info@yorchip.com
Patented Technology
The current Chiplet solutions are focused on Bandwidth and Latest nodes.
Current dominant standard UCIe is focused on HPC and Data Center market.
We have taken the UCIe standard and optimized it for Low Cost, Low Power and novel packaging solutions.
In the current market the Chiplets are used in closed systems and not designed for re-useability across many markets and customers.
Soon, you will be able to focus on your own design and then surround it with off the shelf chiplets - all cost and power optimized for mass markets.
100G Ultra Ethernet Solution Click here
Universal PHY TM News CLICK here
ADC Chiplet News CLICK THIS